"Scalable FPGA graph model to detect routing faults."

Luca Sterpone et al. (2016)

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DOI: 10.1109/IOLTS.2016.7604690

access: closed

type: Conference or Workshop Paper

metadata version: 2019-09-25

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  dblp key:
  - conf/iolts/SterponeCFLSD16
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  - https://dblp.org/rec/conf/iolts/SterponeCFLSD16
Luca Sterpone, Gianpiero Cabodi, Sebastiano F. Finocchiaro, Carmelo Loiacono, Francesco Savarese, Boyang Du:
Scalable FPGA graph model to detect routing faults. IOLTS 2016: 155-160

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