"Gate Sizing for Low Power Design."

Philippe Maurine, Nadine Azémard, Daniel Auvergne (2001)

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type: Conference or Workshop Paper

metadata version: 2004-02-12

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Philippe Maurine, Nadine Azémard, Daniel Auvergne:
Gate Sizing for Low Power Design. VLSI-SOC 2001: 301-312

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