"Speeding Up Verification of RTL Designs by Computing One-to-one ..."

Peer Johannsen, Rolf Drechsler (2001)

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type: Conference or Workshop Paper

metadata version: 2002-08-13

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Peer Johannsen, Rolf Drechsler:
Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. VLSI-SOC 2001: 361-374

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