"Layout-aware high performance interconnects for Network-on-Chip design in ..."

Gursharan Reehal, Mohammed Ismail (2011)

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DOI: 10.1109/IDT.2011.6123102

access: closed

type: Conference or Workshop Paper

metadata version: 2020-11-24

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Gursharan Reehal, Mohammed Ismail:
Layout-aware high performance interconnects for Network-on-Chip design in deep nanometer technologies. IDT 2011: 58-61

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