"Three-phase magnitude-phased-locked loop using FPGA."

A. Gupta (2010)

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DOI: 10.1145/1741906.1742133

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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A. Gupta:
Three-phase magnitude-phased-locked loop using FPGA. ICWET 2010: 976-978

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