"Selective High-Latency Arithmetic Instruction Reuse in Multicore Processors."

Claudiu Buduleci, Arpad Gellert, Adrian Florea (2023)

> Home

Details and statistics

DOI: 10.1109/ICSTCC59206.2023.10308483

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icstcc/BuduleciGF23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icstcc/BuduleciGF23
Claudiu Buduleci, Arpad Gellert, Adrian Florea:
Selective High-Latency Arithmetic Instruction Reuse in Multicore Processors. ICSTCC 2023: 410-415

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.