"Optimized Gate Sizing for Improved Performance and Power Efficiency in ..."

Junyu Jiang (2023)

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DOI: 10.1145/3640115.3640127

access: closed

type: Conference or Workshop Paper

metadata version: 2024-04-01

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Junyu Jiang:
Optimized Gate Sizing for Improved Performance and Power Efficiency in Adder Circuits. ICITEE 2023: 74-78

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