"Novel Method to Generate Tests for VHDL."

Vacius Jusas, Tomas Neverdauskas (2013)

> Home

Details and statistics

DOI: 10.1007/978-3-642-41947-8_31

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icist/JusasN13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icist/JusasN13
Vacius Jusas, Tomas Neverdauskas:
Novel Method to Generate Tests for VHDL. ICIST 2013: 365-375

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.