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"6T SRAM performance and power gain using double gate MOS in 28nm FDSOI ..."

Vivek Asthana et al. (2013)

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DOI: 10.1109/ICICDT.2013.6563310

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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  - conf/icicdt/AsthanaKJHG13
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  - https://dblp.org/rec/conf/icicdt/AsthanaKJHG13
Vivek Asthana, Malathi Kar, Jean Jimenez, Sébastien Haendler, Philippe Galy:
6T SRAM performance and power gain using double gate MOS in 28nm FDSOI technology. ICICDT 2013: 89-92

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