"Novel Design partitioning technique for ASIC prototyping on multi-FPGA ..."

Divyasree Tummalapalli et al. (2022)

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DOI: 10.1109/ICECS202256217.2022.9970882

access: closed

type: Conference or Workshop Paper

metadata version: 2023-06-26

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Divyasree Tummalapalli, Kunapareddy Chiranjeevi, Vikas Akalwadi, Rahul Govindan, Balaji G:
Novel Design partitioning technique for ASIC prototyping on multi-FPGA platforms using Graph Deep Learning. ICECS 2022 2022: 1-4

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