"Simulation of SoCs with embedded mixed-signal Cores using a Verilog ..."

Jan Schat (2006)

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DOI: 10.1109/ICECS.2006.379929

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Jan Schat:
Simulation of SoCs with embedded mixed-signal Cores using a Verilog High-Speed Virtual Serial Interface. ICECS 2006: 878-881

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