"VHDL-AMS modeling of a multi-standard phase locked loop."

Benjamin Nicolle et al. (2005)

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DOI: 10.1109/ICECS.2005.4633374

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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Benjamin Nicolle, Lionel Geynet, Emeric de Foucauld, William Tatinian, Gilles Jacquemod:
VHDL-AMS modeling of a multi-standard phase locked loop. ICECS 2005: 1-4

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