"Automatic methodology for placing the guard rings into chip layout to ..."

Ming-Dou Ker et al. (2001)

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DOI: 10.1109/ICECS.2001.957690

access: closed

type: Conference or Workshop Paper

metadata version: 2021-01-18

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Ming-Dou Ker, Hsin-Chin Jiang, Jeng-Jie Peng, Tzay-Luen Shieh:
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's. ICECS 2001: 113-116

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