"FPGA based realization of a reduced complexity high speed decoder for ..."

Shuja Ahmad Abbasi (2003)

> Home

Details and statistics

DOI: 10.1109/ICECS.2003.1301678

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/icecsys/Abbasi03
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/icecsys/Abbasi03
Shuja Ahmad Abbasi:
FPGA based realization of a reduced complexity high speed decoder for error correction. ICECS 2003: 1002-1005

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.