"At-Speed Logic BIST Architecture for Multi-Clock Designs."

Laung-Terng Wang et al. (2005)

> Home

Details and statistics

DOI: 10.1109/ICCD.2005.119

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

- view
  authority control:
- export record
  dblp key:
  - conf/iccd/WangWHWG05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iccd/WangWHWG05
Laung-Terng Wang, Xiaoqing Wen, Po-Ching Hsu, Shianling Wu, Jonhson Guo:
At-Speed Logic BIST Architecture for Multi-Clock Designs. ICCD 2005: 475-478

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.