"Timing aware partitioning for multi-FPGA based logic simulation using ..."

Subramanian Poothamkurissi Swaminathan, Pey-Chang Kent Lin, Sunil P. Khatri (2012)

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DOI: 10.1109/ICCD.2012.6378634

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Subramanian Poothamkurissi Swaminathan, Pey-Chang Kent Lin, Sunil P. Khatri:
Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening. ICCD 2012: 153-158

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