"YOLO Acceleration using FPGA Architecture."

Guangju Wei et al. (2018)

> Home

Details and statistics

DOI: 10.1109/ICCCHINA.2018.8641256

access: closed

type: Conference or Workshop Paper

metadata version: 2019-04-03

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/iccchina/WeiHCDTY18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iccchina/WeiHCDTY18
Guangju Wei, Yanzhao Hou, Qimei Cui, Gang Deng, Xiaofeng Tao, Yuan Yao:
YOLO Acceleration using FPGA Architecture. ICCC 2018: 734-735

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.