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"Minimal Path Delay Leading Zero Counters on Xilinx FPGAs."
Gregory Morse, Tamás Kozsik, Peter Rakyta (2023)
- Gregory Morse, Tamás Kozsik, Peter Rakyta:
Minimal Path Delay Leading Zero Counters on Xilinx FPGAs. ICCS (3) 2023: 626-640
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