"An efficient delay estimation model for high speed VLSI interconnects."

Mummaneni Kavicharan, Nukala Suryanarayana Murthy, N. Bheema Rao (2013)

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DOI: 10.1109/ICACCI.2013.6637375

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-02

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Mummaneni Kavicharan, Nukala Suryanarayana Murthy, N. Bheema Rao:
An efficient delay estimation model for high speed VLSI interconnects. ICACCI 2013: 1358-1362

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