"Analysis of multi-bit flip flop low power methodology to reduce area and ..."

Saurabh Gautam (2014)

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DOI: 10.1109/ICACCI.2014.6968550

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type: Conference or Workshop Paper

metadata version: 2017-05-24

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Saurabh Gautam:
Analysis of multi-bit flip flop low power methodology to reduce area and power in physical synthesis and clock tree synthesis in 90nm CMOS technology. ICACCI 2014: 570-574

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