"A Parallel Simulated Annealing Approach for Floorplanning in VLSI."

Jyh-Perng Fang et al. (2009)

> Home

Details and statistics

DOI: 10.1007/978-3-642-03095-6_29

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/ica3pp/FangCCLHSH09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/ica3pp/FangCCLHSH09
Jyh-Perng Fang, Yang-Lang Chang, Chih-Chia Chen, Wen-Yew Liang, Tung-Ju Hsieh, Muhammad T. Satria, Chin-Chuan Han:
A Parallel Simulated Annealing Approach for Floorplanning in VLSI. ICA3PP 2009: 291-302

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.