![](https://dblp.uni-trier.de./img/logo.320x120.png)
![search dblp search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
default search action
"1.2V 300MHz CMOS PLL for clock generation in 0.35UM process."
Deana McDonagh, K. I. Arshak, O. Abubaker (2006)
- Deana McDonagh, K. I. Arshak, O. Abubaker:
1.2V 300MHz CMOS PLL for clock generation in 0.35UM process. Communication Systems and Networks 2006: 243-247
![](https://dblp.uni-trier.de./img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.