"Trio: A Triple Class On-chip Network Design for Efficient Multicore ..."

Thomas Canhao Xu et al. (2015)

> Home

Details and statistics

DOI: 10.1109/HPCC-CSS-ICESS.2015.44

access: closed

type: Conference or Workshop Paper

metadata version: 2022-04-09

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/hpcc/XuLLPT15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/hpcc/XuLLPT15
Thomas Canhao Xu, Ville Leppänen, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Trio: A Triple Class On-chip Network Design for Efficient Multicore Processors. HPCC/CSS/ICESS 2015: 951-956

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.