"High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic ..."

Hideki Osaka et al. (2001)

> Home

Details and statistics

DOI: 10.1109/HIS.2001.946695

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

- view
  authority control:
- export record
  dblp key:
  - conf/hoti/OsakaKHW01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/hoti/OsakaKHW01
Hideki Osaka, Toyohiko Komatsu, Susumu Hatano, Takeshi Wada:
High-speed, high-bandwidth DRAM memory bus with crosstalk transfer logic (XTL) interface. Hot Interconnects 2001: 63-67

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.