"Task parallel programming model + hardware acceleration = performance ..."

Tamer Dallou et al. (2016)

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DOI: 10.1109/HOTCHIPS.2016.7936235

access: closed

type: Conference or Workshop Paper

metadata version: 2021-05-03

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Tamer Dallou, Divino Cesar Soares Lucas, Guido Araujo, Lucas Morais, Eduardo Ferreira Barbosa, Michael Frank, Richard Bagley, Raj Sayana:
Task parallel programming model + hardware acceleration = performance advantage. Hot Chips Symposium 2016: 1

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