"Using SystemVerilog assertions to relate non-cycle-accurate to ..."

Hans Eveking, Tobias Dornes, Martin Schweikert (2011)

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DOI: 10.1109/HLDVT.2011.6114161

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/hldvt/EvekingDS11
Hans Eveking, Tobias Dornes, Martin Schweikert:
Using SystemVerilog assertions to relate non-cycle-accurate to cycle-accurate designs. HLDVT 2011: 17-24

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