"Novel architectures for efficient (m, n) parallel counters."

Sreehari Veeramachaneni et al. (2007)

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DOI: 10.1145/1228784.1228833

access: closed

type: Conference or Workshop Paper

metadata version: 2021-10-14

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Sreehari Veeramachaneni, Lingamneni Avinash, Kirthi M. Krishna, M. B. Srinivas:
Novel architectures for efficient (m, n) parallel counters. ACM Great Lakes Symposium on VLSI 2007: 188-191

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