"A parallel VLSI implementation of Viterbi algorithm for accelerated word ..."

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

V. Upadhyaya, Shambhu J. Upadhyaya, Amlan Kundu (1993)

> Home

Details and statistics

DOI: 10.1109/GLSV.1993.224485

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/UpadhyayaUK93
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/UpadhyayaUK93
V. Upadhyaya, Shambhu J. Upadhyaya, Amlan Kundu:
A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition. Great Lakes Symposium on VLSI 1993: 37-41

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.