"A 1.0ns 64-bits GaAs Adder using Quad tree algorithm."

Philippe Royannez, Amara Amara (1996)

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DOI: 10.1109/GLSV.1996.497587

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Philippe Royannez, Amara Amara:
A 1.0ns 64-bits GaAs Adder using Quad tree algorithm. Great Lakes Symposium on VLSI 1996: 24-28

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