"An approach for multilevel logic cell optimization in module generators."

Peter Poechmueller, Manfred Glesner (1991)

> Home

Details and statistics

DOI: 10.1109/GLSV.1991.143980

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/glvlsi/PoechmuellerG91
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/glvlsi/PoechmuellerG91
Peter Poechmueller, Manfred Glesner:
An approach for multilevel logic cell optimization in module generators. Great Lakes Symposium on VLSI 1991: 284-289

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.