"Area minimization algorithm for parallel prefix adders under bitwise delay ..."

Taeko Matsunaga, Yusuke Matsunaga (2007)

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DOI: 10.1145/1228784.1228886

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Taeko Matsunaga, Yusuke Matsunaga:
Area minimization algorithm for parallel prefix adders under bitwise delay constraints. ACM Great Lakes Symposium on VLSI 2007: 435-440

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