"Characterization of the impact of interconnect design on the capacitive ..."

Gerald G. Lopez et al. (2005)

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DOI: 10.1145/1057661.1057672

access: closed

type: Conference or Workshop Paper

metadata version: 2024-10-06

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Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip J. Restle, Mary Yvonne Lanzerotti:
Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI 2005: 38-43

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