"A Tile-based Interconnect Model for FPGA Architecture Exploration."

Chengyu Hu et al. (2020)

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DOI: 10.1145/3386263.3406927

access: closed

type: Conference or Workshop Paper

metadata version: 2025-01-19

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Chengyu Hu, Qinghua Duan, Peng Lu, Wei Liu, Jian Wang, Jinmei Lai:
A Tile-based Interconnect Model for FPGA Architecture Exploration. ACM Great Lakes Symposium on VLSI 2020: 113-118

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