"Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the ..."

Joel Grodstein et al. (2002)

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DOI: 10.1145/505306.505308

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-28

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Joel Grodstein, Rachid Rayess, Tad Truex, Linda Shattuck, Sue Lowell, Dan Bailey, David Bertucci, Gabriel P. Bischoff, Daniel E. Dever, Mike Gowan, Roy Lane, Brian Lilly, Krishna Nagalla, Rahul Shah, Emily Shriver, Shi-Huang Yin, Shannon V. Morton:
Power and CAD considerations for the 1.75mbyte, 1.2ghz L2 cache on the alpha 21364 CPU. ACM Great Lakes Symposium on VLSI 2002: 1-6

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