"CMOS system-on-a-chip voltage scaling beyond 50nm."

Azeez J. Bhavnagarwala et al. (2000)

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DOI: 10.1145/330855.332574

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

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Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl:
CMOS system-on-a-chip voltage scaling beyond 50nm. ACM Great Lakes Symposium on VLSI 2000: 7-12

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