"Circuit/architecture for low-power high-performance 32-bit adder."

Issam S. Abu-Khater et al. (1995)

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DOI: 10.1109/GLSV.1995.516028

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-24

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Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan:
Circuit/architecture for low-power high-performance 32-bit adder. Great Lakes Symposium on VLSI 1995: 74-

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