"Mixed-Level Design Methodology With SystemVerilog Behavior Models for ..."

Wei-Ting Yeh et al. (2023)

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DOI: 10.1109/GCCE59613.2023.10315270

access: closed

type: Conference or Workshop Paper

metadata version: 2023-11-23

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Wei-Ting Yeh, Chung-Lun Chang, Shang-Chih Yin, Chien-Hung Tsai:
Mixed-Level Design Methodology With SystemVerilog Behavior Models for Digitally Controlled Power Converter ICs. GCCE 2023: 1172-1175

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