"Modeling Logic Gates and Circuits with Generalized Nets."

Lenko Erbakanov et al. (2015)

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DOI: 10.1007/978-3-319-26211-6_21

access: closed

type: Conference or Workshop Paper

metadata version: 2021-04-09

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  dblp key:
  - conf/fqas/ErbakanovKPSB15
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  - https://dblp.org/rec/conf/fqas/ErbakanovKPSB15
Lenko Erbakanov, Todor Kostadinov, Todor Petkov, Sotir Sotirov, Veselina Bureva:
Modeling Logic Gates and Circuits with Generalized Nets. IWIFSGN@FQAS 2015: 243-256

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