"Accelerating NFV application using CPU-FPGA tightly coupled architecture."

Yoshikazu Watanabe et al. (2017)

> Home

Details and statistics

DOI: 10.1109/FPT.2017.8280131

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-10

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpt/WatanabeKTHN17
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpt/WatanabeKTHN17
Yoshikazu Watanabe, Yuki Kobayashi, Takashi Takenaka, Takeo Hosomi, Yuichi Nakamura:
Accelerating NFV application using CPU-FPGA tightly coupled architecture. FPT 2017: 136-143

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.