"Evaluation of compact high-throughput reconfigurable architecture based on ..."

Kazuya Tanigawa, Tetsuo Hironaka (2008)

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DOI: 10.1109/FPT.2008.4762396

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-24

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Kazuya Tanigawa, Tetsuo Hironaka:
Evaluation of compact high-throughput reconfigurable architecture based on bit-serial computation. FPT 2008: 273-276

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