"FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding."

Riad Stefo et al. (2001)

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DOI: 10.1007/3-540-44687-7_71

access: closed

type: Conference or Workshop Paper

metadata version: 2024-07-11

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Riad Stefo, José Luis Núñez, Claudia Feregrino, Sudipta Mahapatra, Simon R. Jones:
FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. FPL 2001: 643-647

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