"Performance and Area Modeling of Cmplete FPGA Designs in the Presence of ..."

K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz (2003)

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DOI: 10.1007/978-3-540-45234-8_31

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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K. R. Shesha Shayee, Joonseok Park, Pedro C. Diniz:
Performance and Area Modeling of Cmplete FPGA Designs in the Presence of Loop Transformations. FPL 2003: 313-323

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