"A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for ..."

Paul Saunders, Anthony D. Fagan (2006)

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DOI: 10.1109/FPL.2006.311328

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Paul Saunders, Anthony D. Fagan:
A High Speed, Low Memory FPGA Based LDPC Decoder Architecture for Quasi-Cyclic LDPC Codes. FPL 2006: 1-6

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