Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA."

Eduardo Picatoste-Olloqui et al. (2004)

> Home

Details and statistics

DOI: 10.1007/978-3-540-30117-2_30

access: closed

type: Conference or Workshop Paper

metadata version: 2024-08-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpl/Picatoste-OlloquiCSH04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpl/Picatoste-OlloquiCSH04
Eduardo Picatoste-Olloqui, Francisco Cardells-Tormo, Jordi Sempere-Agulló, Atilà Herms-Berenguer:
Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA. FPL 2004: 279-288

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.