"Power reduction techniques for Dynamically Reconfigurable Processor Arrays."

Takashi Nishimura et al. (2008)

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DOI: 10.1109/FPL.2008.4629949

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Takashi Nishimura, Keiichiro Hirai, Yoshiki Saito, Takuro Nakamura, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano:
Power reduction techniques for Dynamically Reconfigurable Processor Arrays. FPL 2008: 305-310

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