"A novel SEU, MBU and SHE handling strategy for Xilinx Virtex-4 FPGAs."

Xabier Iturbe et al. (2009)

Details and statistics

DOI: 10.1109/FPL.2009.5272410

access: closed

type: Conference or Workshop Paper

metadata version: 2022-01-03

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.