"A Design Flow to Map Parallel Applications onto FPGAs."

Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser (2007)

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DOI: 10.1109/FPL.2007.4380727

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-21

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Sébastien Le Beux, Philippe Marquet, Jean-Luc Dekeyser:
A Design Flow to Map Parallel Applications onto FPGAs. FPL 2007: 605-608

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