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"Find the real speed limit: FPGA CAD for chip-specific application delay ..."

Ibrahim Ahmed et al. (2017)

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DOI: 10.23919/FPL.2017.8056819

access: closed

type: Conference or Workshop Paper

metadata version: 2019-02-18

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  dblp key:
  - conf/fpl/AhmedZTB17
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  - https://dblp.org/rec/conf/fpl/AhmedZTB17
Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz:
Find the real speed limit: FPGA CAD for chip-specific application delay measurement. FPL 2017: 1-8

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