"Post-route LUT output polarity selection for timing optimization."

Kai Zhu (2007)

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DOI: 10.1145/1216919.1216932

access: closed

type: Conference or Workshop Paper

metadata version: 2021-08-11

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Kai Zhu:
Post-route LUT output polarity selection for timing optimization. FPGA 2007: 89-96

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