"A configurable architecture to limit wakeup current in ..."

Assem A. M. Bsoul, Steven J. E. Wilton (2012)

> Home

Details and statistics

DOI: 10.1145/2145694.2145737

access: closed

type: Conference or Workshop Paper

metadata version: 2018-11-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/fpga/BsoulW12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/fpga/BsoulW12
Assem A. M. Bsoul, Steven J. E. Wilton:
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs. FPGA 2012: 245-254

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.